• 168-pin, dual in-line memory module (DIMM)

• PC133-compliant

• Registered inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce loading

• Utilizes 133 MHz SDRAM components

• Supports ECC error detection and correction

• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)

• Single +3.3V power supply

• Fully synchronous; all signals registered on positive edge of PLL clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal SDRAM banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

• Auto refresh mode

• Self refresh mode: 64ms, 4,096-cycle refresh (512MB) or 8,192-cycle refresh (1GB)

• LVTTL-compatible inputs and outputs

• Serial presence-detect (SPD)

• Gold edge contacts