Cisco Systems OC3SGLMDE POS Dynamic Packet Transport Interface Processor Module, p/n: POSIP-OC3-50 (процессорный модуль)

Процессорный модуль Cisco Systems OC3SGLMDE POS Dynamic Packet Transport Interface Processor Module, p/n: POSIP-OC3-50

Описание:

The POSIP-OC3-50 provides a single 155.520-Mbps, Packet OC-3 network interface for Cisco 7000 series and 7500 series routers.

Network interfaces reside on the POSIP-OC3-50 and provide a direct connection between the high-speed Cisco Extended Bus (CxBus or CyBus) and the external networks. The physical layer interface is OC-3.

The POSIP-OC3-50 uses an R5000 central processing unit (CPU), running at 200 Mhz, and comes configured with 32 MB of synchronous dynamic random-access memory (SDRAM) and 4 MB of static random-access memory (SRAM) as the factory default memory configuration. The SDRAM and SRAM on the POSIP-OC3-50 models can be upgraded as your system configuration requires and SRAM and SDRAM memory upgrade options are made available by Cisco Systems.

Packet data is transported using Point-to-Point Protocol (PPP) and is mapped into the STS-3c/STM-1 frame. The encapsulations used add approximately half of the number of bytes of transport overhead as that involved with ATM using ATM Adaptation Layer 5 (AAL5) and line card control (LCC) Subnetwork Access Protocol (SNAP) encapsulations.

The OC-3 interface is compliant with RFC 1619, "PPP over SONET/SDH," and RFC 1662, "PPP in HDLC-like Framing." The POSIP-OC3-50 supports RFC 1619 Point-to-Point Protocol over SONET/SDH encapsulation, and provides support for SNMP agent v1 (RFC 1155-1157), and MIB II (RFC 1213). The POSIP-OC3-50 supports the following features:

• Standards-compliant SONET/SDH interface; SONET/STS-3c and SDH/STM-1 framing and signaling overhead
  
  
• Full-duplex operation at 155 Mbps
  
  
• Intermediate reach optical interface with single-mode fiber
  
  
• Optical interface with multimode fiber
  
  
• Online insertion and removal, enabling you to remove, add, or replace POSIP-OC3-50s on line
  
  
• Microcode is loaded into and operates from synchronous dynamic random-access memory (SDRAM)
  
  
• An R5000 central processing unit (CPU), running at 200 Mhz
  
  
• Support for 16-bit and 32-bit cyclic redundancy checking (CRC-16 and CRC-32, respectively)